In driving a panel, a driving voltage, having a high level for a gate, is generated by a charge pump, which is the most commonly used topology due to low costs and simple implementation compared to a normal boost circuit.
FIG. 1 illustrates a common charge pump circuit 10, wherein diodes D1 to D4 constitute a two-stage charge pump, which is operated using a current pump function of capacitors C1 and C2 through a voltage variation of a DRP pin, to generate a final requested voltage. However, this method has a problem in that it will cause parasitic inductances L1 to L3 to be generated due to outer wiring. Since a simulated supply voltage AVDD has been established during a power-on phase, a large current will pass through the parasitic inductances L2 and L1 when a transistor Q2 turns on and off, resulting in damage to the DRP pin and other logic devices adjusted by pulse widths in a chip.
When the charge pump starts to operate, Q2 turns on. There are two loops 101 and 102. If C1 and C2 are both not being charged, then two loops will be passed through a large current. When Q2 turns off, a large amount of energy will be stored in L1 and L2, resulting in a sudden increase in voltage in the DRP. Then, the parasitic inductances are larger, and the energy is also larger. In addition, parasitic parameters also increase due to the presence of the parasitic inductances.
Therefore, it is necessary to provide an overcurrent protection circuit and a liquid crystal display to solve problems existing in the prior art.